This invention relates to semiconductor memory devices and methods of manufacture, and more particularly to an improved method for making one-transistor dynamic read/write memory devices of the N-channel silicon gate type.
Dynamic read/write memory devices made by the single-level or double-level polysilicon, N-channel, self-aligned processes commonly used in the industry are shown in my U.S. Pat. No. 4,055,444 and my pending application Ser. No. 132,703, filing date Mar. 21, 1980 as well as in U.S. Pat. No. 4,240,092, by C-K Kuo, all assigned to Texas Instruments; these processes are also shown in Electronics: Feb. 19, 1976, pp. 116-121; May 13, 1976, pp. 81-86; and Sept. 28, 1978, pp. 109-116.
In prior dynamic RAM devices, the cell array and peripheral circuitry is usually formed by a process which leaves thick field oxide surrounding MOS transistors of the silicon-gate, self-aligned type on the face of a silicon bar. The field oxide is created in a high-temperature operation using nitride as an oxidation mask; to reduce capacitance between overlying conductors and underlying heavily-doped silicon regions, the field oxide is thick, but the process of growing the oxide results in moat encroachment beneath the edges of the nitride. This is in a continuing problem in large arrays as the capacitor and transistor sizes are scaled down for maximum density.
It is the principal object of this invention to provide an improved high-speed, high-density, dynamic read/write memory device and method of making, particularly for minimizing problems caused by moat encroachment. Another object is to provide a dynamic memory device of reduced cell size yet high speed. An additional object is to provide a high density DRAM memory device, made by an improved method which provides a reduction in capacitance for the peripheral circuitry, compared to the cell array.